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Synchronous dynamic random access memory (SDRAM) is dynamic random
access memory (DRAM) that is synchronized with the system bus. Classic DRAM
has an asynchronous interface, which means that it responds as quickly as
possible to changes in control inputs. SDRAM has a synchronous interface,
meaning that it waits for a clock signal before responding to control inputs
and is therefore synchronized with the computer's system bus. The clock is
used to drive an internal finite state machine that pipelines incoming
instructions. This allows the chip to have a more complex pattern of
operation than an asynchronous DRAM, enabling higher speeds.
Pipelining means that the chip can accept a new instruction before it has
finished processing the previous one. In a pipelined write, the write
command can be immediately followed by another instruction without waiting
for the data to be written to the memory array. In a pipelined read, the
requested data appears after a fixed number of clock pulses after the read
instruction, cycles during which additional instructions can be sent. (This
delay is called the latency and is an important parameter to consider when
purchasing SDRAM for a computer.)
Sizes Mb ranged from 32Mb to about 1Gb.
They were either Single Sided or Dual Sided.
Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10,
and 7.5 ns). Clock rates up to 150 MHz were available for performance
enthusiasts.
They had 168 pin connectors, and 2 notches. |
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